An information handling system (IHS) may include one or more address queues that store information designating memory locations that the IHS should access. Memory may include volatile storage such as system memory and non-volatile storage such as media drives. In the case of volatile storage such as system memory, an IHS typically includes a memory controller with an address queue. An address queue generally includes a number of latches, each latch storing a respective queue entry such as a memory access command. Each memory access command in the queue includes address information that refers to a respective target address or location in the system memory that the memory controller should access. Address queue designers usually desire that a queue be as large as possible to store a maximum number of ready-to-execute memory access commands. Unfortunately, larger queues require more power to operate than smaller queues. Moreover, larger queues consume greater amounts of valuable semiconductor chip real estate than smaller queues.
A typical address queue includes an input that receives queue entries and an output which provides queue entries for execution. More particularly, the address queue input receives a queue entry and stores the queue entry in a respective latch. A queue entry percolates from latch to latch in the queue as it progresses from the queue input to the queue output prior to execution. When system memory includes a number of pages or banks, page mode logic may couple the output of the address queue to the system memory. The page mode logic may combine two memory access commands that exit the output of the address queue to more efficiently access system memory if these two memory access commands reference addresses in the same bank and row of the system memory. While such a page mode logic configuration may improve memory access efficiency, it does not address the size problem of physically large address queues.
What is needed is an address queue apparatus and methodology that addresses the problems above.